(A) Field of the Invention
The present invention relates to an electrostatic discharge protection apparatus. More particularly, it relates to an electrostatic discharge protection apparatus employing a silicon control rectifier.
(B) Description of Related Art
Problems of electrostatic discharge (ESD) are often encountered while in the use and manufacture of integrated circuit (IC). With scaling to down beyond 0.13 um, even 0.1 um, and the increase of demand of high-speed and wide-band wireless ICs, the tiny devices within IC are easy to be destroyed by an instant electrostatic discharging. Therefore, as the IC process continuously forges ahead, highly impact of ESD to the quality of IC is becoming a crucial problem.
The international standard specification of the protection capability of current commercialized IC ESD protection contains 3 categories for regulating the endurance of ESD as from Human Body Model (HBM), Machine Model (MM) and Charged Device Model (CDM), in which the testings must be higher than 2000, 200, 1000 volts in respect of HBM, MM and CDM respectively.
As usual, ESD occurs at an instance of 10 ns to 100 ns. Therefore, an on-chip ESD protection apparatus or circuitry to prevent a chip from being damaged by ESD is extremely necessary.
An excellent ESD protection apparatus has to meet the following requirements: (1) The ESD protection apparatus is off in normal operation; and (2) Instant activation of the ESD protection apparatus once an ESD event happens.
Usually, an ESD protection apparatus is constituted of a main protection apparatus and a secondary protection apparatus. The main protection apparatus undertakes most of the amount of current when an ESD event happens, and the secondary protection apparatus is a circuitry for providing an adequate protection when the main protection apparatus is not completely activated. The main protection apparatus may be a field transistor, an NMOS transistor, a PN diode or a silicon controlled rectifier (SCR), and the secondary protection apparatus may be an MOS transistor with a gate grounded or a diode.
The SCR apparatus is the most efficient one among the aforementioned ESD protection apparatus and provides an efficient ESD protection mechanism to IC chips. When an ESD occurs, the SCR apparatus reduces its impedance instantly and is switched on to share most of the amount of current for providing a reliable and an on-chip protection. Additionally, heat generated under conduction by the SCR can be distributed evenly; therefore the device damage due to localized heat accumulation can be avoided.
The U.S. Pat. No. 5,012,317 discloses an SCR ESD protection apparatus. Referring to FIG. 1, the circuit of the SCR ESD protection apparatus 10 is connected to a bonding pad 102, and a parasitic bipolar pnp transistor 104 is coupled to a resistor 106. When the voltage between the base and emitter of a parasitic bipolar npn transistor 108, coupled to a resistor 110, is greater than a threshold voltage, the parasitic bipolar npn transistor 108 is turned on and conducts current grounding. The current flowing through the parasitic bipolar npn transistor 108 would turn on the parasitic bipolar pnp transistor 104. In return, the current flowing of the parasitic bipolar pnp transistor 104 also accelerates that of the parasitic bipolar npn 108. The kind of positive feedback current between the parasitic bipolar pnp transistor 104 and the parasitic bipolar npn transistor 108, is similar to a characteristic of a pnpn silicon controlled rectifier, which is the well-known latch-up effect. It can be applied in ESD protection apparatus to discharge the electrostatic charge of the bonding pad 102 rapidly.
The structure of the SCR ESD protection apparatus 10 is shown in FIG. 2. An N-well 202, an N+ region 204 and a P+ region 206 are formed in a P-substrate 20, and the N-well 202 contains an N+ region 208 and a P+ region 210. The N+ region 204 and P+ region 206 are grounded, and the N+ region 208 and P+ region 210 are in connection with the bonding pad 102. The pnp bipolar transistor 104 shown in FIG. 1 is constituted of the P+ region 210, the N-well 202 and the P-substrate 20, and the npn bipolar transistor 108 shown in FIG. 1 is constituted of the N+ region 204, the P-substrate 20 and the N-well 202. The base of the pnp bipolar transistor 104 is connected to the collector of the npn bipolar transistor 108, i.e. using the common N-well 202, in forming the aforementioned pnpn silicon controlled rectifier.
FIG. 3 shows a current vs. voltage (I-V) characteristic curve of the SCR ESD protection apparatus 10. The SCR ESD protection apparatus 10 is off before the latch-up occurs. When an applied voltage is higher than a xe2x80x9ctriggering voltagexe2x80x9d, the latch-up is activated to reduce the voltage to a xe2x80x9cholding voltagexe2x80x9d as a protection mechanism. Most of the amount of current is rapidly discharged by virtue of the pnpn structure.
Obviously, the triggering voltage and the holding voltage are two main factors relative to the characteristics of the SCR ESD protection circuit 10. (1) If the triggering voltage is too high, the device to be protected may be damaged because the SCR ESD protection apparatus 10 is not activated in time; (2) if the triggering voltage is too low, the SCR ESD protection apparatus 10 is easily activated by an exterior noise of the device; (3) if the holding voltage is too high, the device to be protected may be damaged due to heat concentration caused by the high power consumption at the high holding voltage; and (4) if the holding voltage is too low, the SCR ESD protection apparatus 10 is easily activated by an exterior noise of the protected device.
The U.S. Pat. No. 6,172,404 discloses an SCR which separates the parasitic bipolar pnp transistor 104 and the parasitic bipolar npn transistor 108 to increase the holding voltage, thereby inducing the parasitic bipolar pnp transistor 104 not turned on completely.
The U.S. Pat. No. 5,465,189 discloses a low triggering voltage SCR ESD protection circuitry, whose triggering voltage is equivalent to the breakdown voltage of the IC and normally is around 12 volts.
To sum up, the importance of the triggering voltage and holding voltage is well acknowledged, but their implementations are troublesome due to various requirements of different chips.
The object of the present invention is to provide an adjustable electrostatic discharge apparatus to prevent the device damage caused by inadequate triggering voltage and holding voltage. The electrostatic discharge apparatus employs an SCR, a triggering voltage adapter network for triggering voltage adjustment and a holding voltage adapter network for holding voltage adjustment to change the I-V characteristic of the protected device. The SCR ESD protection apparatus of the present invention provides the capability of adjustment so as to meet various requirements of different kinds of chips.
The first embodiment of an electrostatic discharge apparatus of the present invention comprises a first conductive type substrate, a gate, a triggering voltage adapter network and a holding voltage adapter network, and a holding voltage adapter network in which the substrate including a first region exhibiting a second conductive type, a second region exhibiting the first conductive type, a third region exhibiting the second conductive type, a fourth region of the first conductivity within the first region, a fifth region exhibiting the second conductive type contained in the first region and a sixth region exhibiting the second conductive type on the boundary of the first region and between the third region and the fifth region. The gate is on the surface of the substrate between the third region and the sixth region. The triggering voltage adapter network is in connection with the second region, the third region, the fourth region and the gate, and the holding voltage adapter network is in connection with the second region, the third region, the fourth region and the fifth region.
The first embodiment of an electrostatic discharge apparatus of the present invention may further comprise a seventh region of a second conductive type within the first region to be the second embodiment, in which the triggering voltage adapter network and the holding voltage adapter network are further electrically connected to the seventh region.
The third embodiment of an electrostatic discharge apparatus of the present invention comprises a substrate exhibiting a first conductive type, a gate, a triggering voltage adapter network and a holding voltage adapter network, in which the substrate including a first region exhibiting a second conductive type, a second region exhibiting the first conductive type, a third region exhibiting the second conductive type, a fourth region exhibiting the first conductive type within the first region and a fifth region exhibiting the second conductive type positioned on the boundary of the first region and between the third region and the fourth region. The triggering voltage adapter network is in connection with the second region, the third region, the fourth region and the gate. The holding voltage adapter network is in connection with the second region, the third region, the fourth region and the fifth region.
The third embodiment of an electrostatic discharge apparatus of the present invention may further comprise a sixth region of a second conductive type within the first region to be the fourth embodiment, in which the triggering voltage adapter network and the holding voltage adapter network are further electrically connected to the sixth region.
In the above embodiments, the first conductivity is P-type and the second conductivity N-type. The triggering voltage and holding voltage adapter networks are constituted of a circuit of resistor-capacitor (RC) coupling type, capacitor type or diode type.
The triggering voltage and holding voltage adapter network can be used in combination or individually to adjust the triggering voltage and holding voltage in accordance with various requirements.